On a fixed synthetic sign-off board, 8/8 fixture-authored SVA properties were PROVEN. Only 5/8 passed our proof-quality audit. That is the gap Proof Firewall was built to expose. A green formal result can still rest on a condition the design never reaches, or on an assertion too weak to catch a relevant broken variant. In this fixed synthetic fixture, one proof was `VACUOUS` and two were `WEAK`. The practical test for a verification lead is whether a property constrains behavior the design can actually reach and detects a meaningful failure when that design is changed. We built the audit after the formal result. It checks whether the condition ever occurs and whether the assertion catches relevant broken versions of the design. A proof that fails either check is held for human review with a reason instead of being filed as sign-off evidence. The video shows the 8/8-to-5/8 reversal. What evidence does your team ask for before a green assertion enters the sign-off package? #FormalVerification #SystemVerilog #SemiconductorVerification #AIGovernance