On our synthetic board, 8/8 proofs were green. A second review kept only 5/8 in the sign-off file. 🟢 That is the visual reversal behind Proof Firewall, our demo for verification teams working with AI-assisted SVA. The bare flow marks all eight fixture-authored SystemVerilog assertions `PROVEN`. After review, five are `TRUSTWORTHY`; one is `VACUOUS` and two are `WEAK`. `ARB3` shows why. Its input condition can never happen in the synthetic arbiter, so the proof can pass without testing the behavior it appears to cover. AI can help author assertions. Before tape-out sign-off, the proof record still needs a reason a reviewer can inspect. Which proof fields have made it into your team's sign-off template so far? #FormalVerification #SystemVerilog #DesignVerification #SemiconductorEngineering